1. Field of the Invention
The present invention relates to image processors, and more particularly, to a real-time encoder in an H.264 compression coding system.
2. Description of the Background Art
A video recorder of a background art is described in JP2010-272993A. In the video recorder, multiple video data sets input from a video input unit are stored in a frame buffer. An encoding unit encodes video data. An encoder control unit allots encoding time to each of the video data sets stored in the frame buffer. Then when time allotted to a currently target video data set of the encoding unit lapses, the target video data set is switched to the next set.
H.264 real-time encoders generally perform header processing by software processing employing, for example, a CPU, and perform macroblock processing by hardware processing employing, for example, a hardware accelerator. This is because software processing is effective for header processing as it can be flexibly adapted to various profiles and application programs, while hardware processing is effective for macroblock processing that involves huge amount of computing including a lot of repeated routine operations.
Encoding by both software processing and hardware processing, however, causes issuance of commands from a CPU to a hardware accelerator and notification signifying a completion of processing (interrupt notification) from a hardware accelerator to a CPU, every time processing of one picture is complete. Thus issuance of commands and interrupt notifications frequently occurs between the CPU and the hardware accelerator, and in consequence, the processing load of the CPU increases and waiting time is prolonged, resulting in a protracted time required for encoding as a whole.